1. Field of the Invention
This invention relates to design of integrated circuits, and more particularly to inclusion of probe cells in an integrated circuit design for probing of the integrated circuit.
2. Description of the Related Art
During manufacture of an integrated circuit (e.g., a microprocessor), electronic components are formed upon and within a frontside surface of a semiconductor substrate having opposed frontside and backside surfaces. The electronic components are connected together by electrically conductive interconnect lines referred to as signal lines, forming an electronic circuit. Signal lines, for connecting to external devices, may be terminated at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit, also referred to as chip, is typically secured within a protective semiconductor device package (e.g., carrier). Each I/O pad of the chip is then connected to one or more terminals of the device package. The terminals of a device package may be arranged in a two-dimensional array across an underside surface of the device package or may be arranged about the periphery of the package. The I/O pads of the chip are electrically connected to the terminals of the device package. Conductive bumps are used with some types of device packages to connect the I/O pads of the underside surface of the chip to the terminals. Wire connections are used with other types of device packages to connect the I/O pads of the chip to the terminals using wire bonding technology. The chip may be attached to another semiconductor substrate, a printed circuit board (PCB), or a carrier using a variety of methods and technologies.
As integrated circuit fabrication technology has improved, manufacturers have been able to integrate more and more functions onto single silicon substrates. As the number of functions on a single chip has increased, however, the number of signal lines which need to be connected to external devices has also increased. The corresponding numbers of required I/O pads and device package terminals have increased as well, as have the design and testing complexities of the chips, device packages and PCBs. As integrated circuit fabrication technology advances, various chip packaging techniques are being proposed and adopted to specifically address issues resulting from the continual increase of functions on a single chip.
One chip packaging technology adopted is a grid array semiconductor device package having terminals arranged in a two-dimensional array across an underside surface of the device package. FIG. 1 illustrates a cross-section view of one type of grid array device package, an exemplary ball grid array (BGA) device 10 including an integrated circuit 12 mounted upon a larger package substrate 14. Substrate 14 includes two sets of bonding pads: a first set of bonding pads 16 on an upper surface adjacent to integrated circuit 12 and a second set of bonding pads 18 arranged in a two-dimensional array across an underside surface. Integrated circuit 12 includes a semiconductor substrate 20 having multiple electronic components formed within a circuit layer 22 upon a frontside surface of semiconductor substrate 20 during wafer fabrication. The electronic components are connected by electrically conductive signal lines, forming an electronic circuit. Multiple I/O pads 24 are also formed within circuit layer 22. I/O pads 24 are typically coated with solder, forming solder bumps 26.
The integrated circuit 12 is attached to the package substrate 14 using a controlled collapse chip connection (C4) or flip chip packaging method. Flip chip packaging may also be referred to as Direct Chip Attach (DCA) since the chip may be directly attached to substrates, PCBs, or carriers. During a flip chip mounting operation, solder bumps 26 are placed in physical contact with corresponding members of the first set of bonding pads 16. Solder bumps 26 are then heated long enough for the solder to reflow. When the solder cools, I/O pads 24 of integrated circuit 12 are electrically and mechanically coupled to the corresponding members of the first set of bonding pads 16 of the package substrate 14. After integrated circuit 12 is attached to package substrate 14, the region between integrated circuit 12 and package substrate 14 may be filled with an “underfill” material 28 which encapsulates the connections of the chip and provides other mechanical advantages.
Package substrate 14 may be made of, for example, fiberglass-epoxy printed circuit board material or ceramic material (e.g., aluminum oxide, alumina, Al2O3, or aluminum nitride, AlN). Package substrate 14 includes one or more layers of signal lines referred to as interconnects, which connect respective members of the first set of bonding pads 16 and the second set of bonding pads 18. Members of the second set of bonding pads 18 function as device package terminals and are coated with solder, forming solder balls 30 on the underside surface of package substrate 14. Solder balls 30 allow BGA device 10 to be surface mounted, for example, to an ordinary PCB. During PCB assembly, BGA device 10 is attached to the PCB by reflow of solder balls 30 just as the integrated circuit is attached to the package substrate 14. Other flip chip-in-package solutions, such as chip scale packages (CSP), may be used instead of BGA to attach an integrated circuit to device packages. The integrated circuit may also be attached directly to a PCB (e.g., no device package) and then encapsulated for protection as a flip chip-on-board.
Following manufacture, the chip may be tested to ensure the integrated circuit will perform as designed. Some integrated circuits may be probed from the frontside for testing. However, the flip chip mounting of integrated circuit 12 to package substrate 14 prevents physical access to circuit layer 22 for failure analysis and fault isolation during test. When a chip fails or when testing of the chip is performed, access to electronic components of the chip may only be possible from the backside of the device. Thus, several analytic and diagnostic techniques developed to reveal defects and logic states within integrated circuits have become useful when applied to flip chip packaged integrated circuits such as the integrated circuit 12 in BGA 10. One of these techniques is backside probing. Backside probing involves making electrical contact to probe certain nodes of the integrated circuit. When backside probing an integrated circuit, the chip is typically accessed by one or more probes configured to make electrical contact with backside probe locations on the chip which connect to nodes of the integrated circuit. The nodes of the integrated circuit may then be probed from the backside of the chip. The integrated circuit may be analyzed by activating or measuring the nodes of the integrated circuit through a backside test device.
Probe locations are typically added during the physical layout of the integrated circuit. However, it may be difficult to rearrange congested areas of the integrated circuit to make room for probe locations. In addition, if probe locations are added for every node, unnecessary delay may be added to many nodes of the integrated circuit.